1/7 september 1999 AN1155 application note connecting the st10 microcontroller to m29 series flash memories contents n introduction n advantages of flash n flash bus architecture n st10f163 bus architecture n timing requirements n conclusion introduction this application note describes specifically the connection of an m29f400b flash memory to an st10f163 microcontroller, although it can also be used as a reference for other flash memory devices and other microcontrollers. the application note discusses the bus architectures of the flash and the st10. the additional features of the flash, reset/block tem- porary unprotect and ready/busy output are also discussed. the information in this application note is useful to hardware engineers who are about to design a new circuit using a flash memory. advantages of flash flash memories can be used to store both code and data for microprocessors in the st10 family. the st10 can be config- ured to boot from the flash and to execute the application soft- ware from it. unlike eprom, flash can be used to store data; the st10 can erase old, unwanted data and replace it. the ap- plication software can also be updated so that field upgrades can be performed without disassembling the product. the st10f163 contains 128kbytes of internal flash. the inter- nal flash can contain the program code that the microcontroller runs. however, the internal flash cannot always be used for data storage because: 1. the internal flash has a program/erase endurance of only 1000 cycles and it is therefore not suitable for frequent up- dates. 2. programming and erasing the internal flash requires 12v to be applied to the st10 and a 12v supply is often not available. 3. interrupts cannot be run from the internal flash while it is programming or erasing. hard real-time systems may not be able to tolerate the system becoming unavailable for 1 sec- ond or more while the internal flash is erasing. putting an additional flash memory on to an st10f163 allevi- ates these problems. extra space can be provided for code and data and the system can continue to be powered from a single 5v supply. additionally the code can be run from the internal flash while the external flash is updated. interrupts and high- priority tasks can run from the internal flash while the external flash is programming or erasing. access to data in the external flash is possible during erase operations using the erase sus- pend feature of the m29f400b.
AN1155 - application note 2/7 flash bus architecture take a look at the bus on the m29f400b, figure 1 shows the logic diagram. the memory has separate address and data buses (de-multiplexed in the st10 terminology). the control lines are chip enable (e ), output enable (g ) and write enable (w ). also, ready/busy output (rb ) and reset/block temporary unprotect (rp ) are present. finally there is the byte pin that selects 8-bit or 16-bit mode. figure 1. m29f400b logic diagram the m29f400b has been designed to allow byte to change between accesses, so 8-bit accesses and 16-bit accesses can be achieved in the same design. in practice it is far simpler to always use the memory in one mode; in order to swap modes additional logic is required to decode the dq15aC1 pin, this would complicate the design, add cost and probably increase the wait-states required to access the memory. in the example here 16-bit mode has been chosen. it is possible to read 8-bits in at a time, but it may be necessary to implement a trap on the st10 in order to do this. all write accesses will write 16-bits at a time. in order to change one byte in the memory it will be necessary to write a word. programming words and bytes takes the m29f400b the same amount of time; the internal charge pumps required for the pro- gram operation are word-wide, not byte-wide. once the choice has been made to keep byte high, the special pin, dq15aC1, can be treated like any other data input/output pin. it forms part of the data bus, dq0-dq15. note that the a0 address pin on the m29f400b specifies the address of a word, not of a byte; the address bus of the st10f163 will need to be shifted compared to the address bus of the m29f400b in order to address the flash correctly. the reset/block temporary unprotect pin (rp ) accepts three states: reset (v il ), not reset (v ih ) and block temporary unprotect (v id ). reset and not reset are the usual signals for a reset line. the st10f163 provides these two signals on its rstout pin. the third state, block temporary unprotect is used to temporarily unprotect blocks that have been specifically protected in the memory. many applica- tions do not protect any blocks and therefore connect the rp pin directly to the system reset signal. figure 2 gives an example of how the connection between the st10f163s rstout pin and the m29f400bs rp pin can be made. the circuit makes use of a jumper to enable block temporary unpro- tect. many applications will provide the 12v from an external source, in which case the jumper can be re- placed by a connector. the advantage with the circuit, as it stands, is that a reset from the st10 will override block temporary unprotect and cause the flash to reset. only four additional components are required. ai02904 18 a0-a17 w dq0-dq14 v cc m29f400bt m29f400bb e v ss 15 g rp dq15aC1 byte rb
3/7 AN1155 - application note figure 2. reset/block temporary unprotect circuit before the jumper is inserted, and when rstout is high, v ih , rp is connected to 5v through the 10k w resistor and the diode. the current required by rp is very low, in the order of 1 m a at 5v. the voltage drop in the resistor and the diode at these currents will keep rp very close to 5v. when the jumper is fitted the diode ceases to conduct and rp rises to 12v as the capacitor charges. the time-constant of a 10k w re- sistor and a 50pf capacitor is 500ns, satisfying the t phphh rise-time requirements of the m29f400b. dur- ing a reset, rstout is low, v il , and the jfet is switched on, bringing rp close to ground. the current consumption during a reset rises due to the current through the 10k w resistor. although the use of a jumper may not be the most elegant solution, it is a practical one because it main- tains the security level offered by the block protection. there is little point in having the block temporary unprotect pin under software control. the whole point of the block protection feature is to protect against software failure. allowing the block temporary unprotect feature to be under the control of software is nearly equivalent to not protecting the blocks in the first place. the ready/busy output (rb ) provides a simple mechanism for determining if the flash is busy or not. by connecting the ready/busy pin up to an interrupt line of the microcontroller it is possible to program the flash under interrupt control, freeing the st10 to perform other tasks while the flash is programming. oth- erwise the flash must be polled in order to find out if program or erase operations have completed. ready/ busy is an open drain output and, therefore, requires a pull-up resistor to bring the line up to v cc when the flash is ready. one situation that the software must be aware of is the error situation. when a program or erase error occurs ready/busy will remain low until the error is cleared. a timer, or polling algorithm, should be used to catch this situation and deal with it correctly. ai02933 10k w 50pf 5v 12v rstout rp
AN1155 - application note 4/7 st10f163 bus architecture the st10f163's bus architecture allows for both multiplexed buses and de-multiplexed buses. the sim- plest connection to the m29f400b is using a de-multiplexed bus. the address bus is on port 1 (a0-a15) and port 4 (a16-a23). the data bus is on port 0 (d0-d15). the st10f163 provides external memory write strobe (wr ) and external memory read strobe (rd ) signals. these are directly compatible with the write enable (w ) and output enable (g ) required by the m29f400b. there are also five chip selects (cs0 -cs4 ). cs1 has been used here to control accesses to the m29f400b's chip enable (e ), though any of the other four would work similarly. the connection between the st10f163 and the m29f400b can be achieved without additional glue logic. figure 3 shows the connection diagram. figure 3. connection between the st10f163 and the m29f400b note that the connection between the flash memory address bus and the st10f163 address bus is shift- ed. a0 on the st10f163 is not connected to the flash memory as this bit of the address bus selects be- tween the lsb and the msb. the flash memory only outputs word-width values, each increment in the flashs address space selects the next word. to make the two address buses compatible a1 on the st10f163 should be connected to a0 on the flash memory; a2 on the st10f163 should connect to a1 on the flash memory; etc. the highest st10f163 memory address bit used is a18, which connects to a17 on the flash. the higher address bits are not required (for example for address decoding) since the address decode logic is internal to the st10f163 and cs1 is used to enable the flash. ai02932 18 a0-a17 w dq0-dq14 m29f400bt m29f400bb e g rp dq15aC1 byte rb 15 3 v cc port 0, ad0-ad15 port 1, a1-a15 port 4, a16-a18 st10f163 rstout rd wr cs1 v cc 10k w port2, ex0in reset/block temporary unprotection circuit
5/7 AN1155 - application note timing requirements the st10f163 bus is very adaptable, allowing for changes to wait-states, read/write delays, chip select delays and tri-state delays. the timings are shown with the st10 configured for unlatched csx, read/ write delay, normal ale and no tri-state delay. the wait-states are determined by t a (address set-up wait-states), t c (cycle wait-states) and t f (tri-state wait-states). in all cases t a = 0ns and t f = 0ns. one wait- state with f cpu = 25mhz gives t c = 40ns, otherwise t c = 0ns (zero wait-states). table 1 shows the principal read timing requirements of the m29f400b and the read timings generated by the st10f163 (inapplicable timings have been left out). figure 4 shows the principal read timing wave- forms. table 2 shows the principal write timings and figure 5 the principal write timing waveforms. table 1. principal read timing requirements figure 4. principal read timing waveforms m29f400b st10f163 symbol 45 55 70 f cpu = 25mhz t c = 0ns f cpu = 25mhz t c = 40ns f cpu = 20mhz t c = 0ns t avav 45 55 70 80 120 100 t av qv 45 55 70 50 90 70 t elqv 45 55 70 50 90 70 t glqv 25 30 30 20 60 30 t ghqz 15 18 20 26 26 36 t oh 000 0 0 0 ai02942 tavav tavqv tglqv toh a0-a17 g dq0-dq15 e telqv tghqz data out
AN1155 - application note 6/7 the 45ns access time m29f400b cannot satisfy all of the timing requirements of the st10f163 at 25mhz with zero wait-states: t glqv , t wlwh , t dvwh and t wlax all miss the st10f163 timing requirements. intro- ducing one wait-state allows all of the timing requirements to be comfortably satisfied by the 70ns part. reducing the st10f163 clock speed to 20mhz also allows all of the timing requirements to be satisfied by the 55ns part, but without any margin. table 2. write timing requirements, write enable controlled figure 5. principal write timing waveforms conclusion the m29f400b, and other flash memory parts from stmicroelectronics, can be easily connected to the st10f163 using no glue logic. zero or one wait-state solutions can be realized. the block temporary un- protect feature can be designed in easily and the software overhead for programming the flash can be reduced by connecting the ready/busy output pin to an interrupt line. m29f400b st10f163 symbol 45 55 70 f cpu = 25mhz t c = 0ns f cpu = 25mhz t c = 40ns f cpu = 20mhz t c = 0ns t avav 45 55 70 80 120 100 t wlwh 40 40 45 30 70 40 t dvwh 25 25 30 20 60 30 t whwl 20 20 20 40 40 50 t wlax 40 40 45 30 70 40 ai02946 tavav twlwh tdvwh a0-a17 w, wr dq0-dq14 dq15aC1 e, cs1 twhwl data in twlax
7/7 AN1155 - application note if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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